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MINIMIZATION OF NETWORKS WITH COMPLEX GATES

Craig Files, Andre Reis, Marek A. Perkowski, Michel Robert, Daniel Auvergne

Abstract

This paper describes a top-end minimization algorithm that is used to optimize a complex gate network. The basis for this approach, is the use of a library-free layout generator, instead of a standard pre-characterized library, such as the traditional layout synthesis method of standard-cells. The library-free cells are made up of static CMOS complex gates, where the quality of the final layout is based on the initial network (input to the layout generator). That is, if the initial network is given in a form that cannot be easily implemented in complex gates, then the final layout will not be good. In this paper, we present a method that produces "high-quality" initial networks, using a new approach based on minimizing the complex gates.

Mathematically, a complex gate is one that realizes a negation of an arbitrary positive unate function. This paper describes a method of minimization of single-output, two-level networks from unlimited complex gates, implemented in the program COMPLEX. This program is used as a preprocessor to TROPIC, a automatic layout generator. The presented method is applied to completely specified functions to minimize the number of gates, variables, transistors and values of other parameters.



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19. Februar 1997